Data processing circuits often include memory circuits for the storage of instruction code and data in binary form. In memory structures such as Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs), the data is accessed via a read operation, and the data can be replaced with new data via a write operation. A portion of the memory block, or cell, to be read or written is selected using address signals, wherein decoding of the address signals is used to generate row-select signals that select the particular portion of the memory, or memory cell. Read and write operations are controlled by a clock signal which synchronizes timing and a control signal which determines whether a read or write operation is to take place.
In a data processing circuit that is highly optimized for speed, the time required to access the memory is crucial to the performance of the circuit. The speed of operation of a memory circuit can be measured relative to the period of the clock signal, wherein multiple periods, or cycles, of the clock signal may be required for a read or write operation. In some instances, one clock cycle is used to set up the address, control, and data signals, and the following clock cycle is used to perform the operation. In a more optimized technique, the second half of a cycle is used for setting up the address, control, and data signals, and the first half of the following cycle is used to perform the operation. This more optimized technique, which will be referred to as "cycle-stealing" requires only a single clock cycle (two-consecutive half-cycles) for each operation.
The access time of the memory is an important timing parameter for a read operation. In the case where the second half of the clock cycle is used to set up the address and control signals, the access time would be measured from the rising edge of the clock signal, which corresponds to the beginning of the clock cycle in which the operation is occurring. The access time is defined as the time between the rising edge of the clock signal and the appearance of valid data at the data outputs of the memory.
In order to minimize the access time of a memory circuit, the address signals are often pre-decoded such that the row-select signals produced by decoding the address signals are at their desired levels when the read operation begins. In a system using the cycle-stealing technique, having the row-select signals valid at the rising edge of the clock signal reduces the access time of a read operation, but two types of problems can arise during a write operation.
First, if the row-select signals propagate through the memory circuit more quickly than the control signal, a false read operation occurs when a write operation is intended. In most memory circuits, the write operation does correctly occur once the control signal propagates to the portion of the memory being selected, but excess power is consumed by the false read operations.
Second, if the control and row-select signals propagate to the portion of the memory being selected before the new data to be written is valid, false data is written to the cell. In most memory circuits, the correct data is written to the cell once the new data becomes valid, but once again, excess power is consumed by the false write operations.
Therefore, a need exists for a method and apparatus for reducing power consumption in memory circuits by eliminating false read and false write operations, while having a minimal effect on read operation access time.